Dielectric-polysilicon-dielectric antifuse for field programmable logic applications

ABSTRACT

A novel antifuse structure includes a novel antifuse material layer comprises a first dielectric layer, a first polysilicon layer (which may optionally be lightly doped) disposed over the first dielectric layer, and a second dielectric layer disposed over the first polysilicon layer. The dielectric layers may be formed of silicon nitride, silicon dioxide, silicon oxynitride and combinations of the foregoing. Additional layers may also be included to form D/P/D/P/D, D/P/D/a-Si/D sandwiches, and the like. The polysilicon layer provides the ability to control the breakdown voltage of the antifuse through control of the doping level while maintaining a relatively large thickness of the antifuse material layer resulting in low capacitance for the antifuse. The antifuse material layer is compatible with high temperature processes (500° C.-950° C.) and may be carried out in the range of 400° C.-950° C. making it compatible with a wide range of processes.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional of patent application Ser. No. 08/289,114, filedAug. 11, 1994, now U.S. Pat. No. 5,581,111, which is a continuation inpart of application Ser. No. 08/088,298, filed Jul. 7, 1993, now U.S.Pat. No. 5,449,947.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of semiconductortechnology. More specifically, it relates to one-time electricallyprogrammable antifuse technology for use in field programmable logicapplications. Still more specifically, the present invention is directedto a novel antifuse and method of fabricating such a novel antifuse.

2. The Prior Art

Numerous processes for the fabrication of antifuses are known in theart. Some of these processes may easily be integrated into alreadyexisting integrated circuit fabrication processes. Some antifuseelements incorporate a dielectric antifuse material which contains anitride or oxide material such as silicon nitride ("SIN") or silicondioxide ("SiO₂ "), either as a single layer, or as a part of amultilayer dielectric such as those described in U.S. Pat. No. 4,823,181to Mohsen et al., entitled PROGRAMMABLE LOW IMPEDANCE ANTIFUSE ELEMENTand U.S. Pat. No. 4,899,205 to Hamdy et al., entitledELECTRICALLY-PROGRAMMABLE LOW-IMPEDANCE ANTI-FUSE ELEMENT. Such antifusestructures exhibit excellent leakage and reliability characteristics,and are thus preferred for user-programmable antifuse applications.

Polysilicon ("Poly")/Oxide-Nitride-Oxide("ONO")/N+ diffusion antifusehas long been a primary choice for production antifuse structures.Essentially it consists of a top electrode formed of Poly, an antifusematerial layer consisting of a sandwich of SiO₂, SiN, and SiC₂ and alower antifuse electrode consisting of an N+ diffusion region.Unfortunately, as the demand for higher density devices and, hence, asmaller antifuse structure forces the construction of smaller antifuses,this process has not proved highly scalable in both the antifusematerial layer thickness (which determines breakdown or programmingvoltage of the antifuse) and the width of the antifuse cell. This ismanifested as follows: when the active antifuse cell opening isenlarged, the defect density of the product with the same antifusepopulation increases. The defect density of the product also increaseswhen the antifuse thickness is shrunk and the bottom oxide of theantifuse is grown over the N+ diffusion area. The present invention isdirected toward reducing the problems arising from the scaling down ofcurrent ONO-based antifuse technology and providing the neededperformance and reliability for next generation antifuse process.

OBJECTS AND ADVANTAGES OF THE INVENTION

Accordingly, it is an object of the present invention to provide anantifuse and process for making same which can be scaled down in size to0.6 μm and below without increase in defect rate and without requiringexotic process steps.

It is a further object of the present invention to provide an antifusestructure and process for making same which has reduced capacitance overequivalent ONO-type antifuses.

A further object of the present invention is to provide an antifusestructure and a method of making same which has reduced capacitance, ahigher thickness of the antifuse material layer, without the necessityfor increasing the breakdown or programming voltage of the antifuse.

A further object of the present invention is to provide an antifusestructure and a method of making same which can be carried out withrelatively high temperature process up to about 950° C. or by rapidthermal processing (RTP).

A further object of the present invention is to provide an antifusestructure and a method of making same which has an antifuse materiallayer formed of a dielectric/Poly/dielectric sandwich resulting in anantifuse material layer exhibiting much more favorable or no timedependent dielectric breakdown ("TDDB") behavior during circuitoperation.

Yet a further object of the present invention is to provide an antifusestructure and a method of making same which has increased reliabilitydue to the presence of a doped Poly layer in the middle of the antifusematerial layer sandwich.

These and many other objects and advantages of the present inventionwill become apparent to those of ordinary skill in the art from aconsideration of the drawings and ensuing description of the invention,

SUMMARY OF THE INVENTION

In accordance with the present invention a novel antifuse material layercomprises a first dielectric layer, a first polysilicon layer (which mayoptionally be lightly doped) disposed over the first dielectric layer,and a second dielectric layer disposed over the first polysilicon layer.The dielectric layers may be formed of silicon nitride, silicon dioxide,silicon oxynitride and combinations of the foregoing. Additional layersmay also be included to form D/P/D/P/D, D/P/D/a-Si/D sandwiches, and thelike. The polysilicon layer provides the ability to control thebreakdown voltage of the antifuse through control of the doping levelwhile maintaining a relatively large thickness of the antifuse materiallayer resulting in low capacitance for the antifuse. The antifusematerial layer is compatible with high temperature processes (500°C.-950° C.) and may be carried out in the range of 400° C.-950° C.making it compatible with a wide range of processes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a figure of an antifuse in accordance with a first preferredembodiment of the present invention.

FIG. 2 is a figure of an antifuse in accordance with a second preferredembodiment of the present invention.

FIG. 3 is a figure of an antifuse in accordance with a third preferredembodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Those of ordinary skill in the art will realize that the followingdescription of the present invention is illustrative only and is notintended to be in any way limiting. Other embodiments of the inventionwill readily suggest themselves to such skilled persons from anexamination of the within disclosure.

With reference to FIG. 1, antifuses 10 are basic microcircuit componentswhich comprise a bottom electrode 12, an antifuse material layer 14, anda top electrode 16. In use, they are one-time programmable elementswhich start out life as representing an open circuit between the bottomelectrode 12 and the top electrode 16. Antifuses may be programmed tothe conducting state by applying a voltage across the top and bottomelectrodes in excess of the breakdown voltage of the dielectric antifusematerial layer 14. When a breakdown voltage is applied, the antifusematerial layer ruptures and a conductive link is formed in the rupturezone to conduct electrical current between the bottom and topelectrodes.

Some prior art antifuses make use of a top and a bottom electrode formedof a metal. While beneficial in many respects, such metal-to-metalantifuses present some difficulties in manufacturing, among them theneed to conduct the process of fabricating the device containing themetal-to-metal antifuse at a temperature of less than about 420° C. inorder to prevent damage to the metal electrodes. This damage would ariseif the lower metal electrode were processed much above about 420° C. dueto diffusion into underlying structures of the semiconductor.

Some prior art antifuses make use of an antifuse material layer formedof a sandwich of ONO, others make use of pure dielectrics based antifusematerial layers (e.g., oxide, nitride, etc.). While fit for theirintended purposes, such antifuse material layers can exhibit TDDBbehavior which manifests itself as a device failure occurring after thedevice has left the factory and after it has tested good. Thus TDDBpresents a serious reliability problem to the use of devicesincorporating antifuses.

The present invention is directed to a new type of antifuse materiallayer which can be used in a number of types of antifuses. It provides ahigh resistance to TDDB behavior, does not require the use of exoticprocess steps, and can be carried out over a wide range of temperatures(from about 400° C. to about 950° C.) yielding the ability to use morereliable high temperature processing for a more reliable antifuse.

In accordance with the present invention, antifuse material layer 14 isreplaced with an antifuse material layer comprising a sandwich formed ofa dielectric/Poly/dielectric ("D/P/D"). The D/P/D antifuse materiallayer is programmable over a range of about 6 volts-100 volts dependingupon the materials and thicknesses used as would be known to those ofordinary skill in the art. The D/P/D antifuse material layer may besubstituted in metal-to-metal antifuses as well as Poly to Polyantifuses or Poly to diffusion antifuses. As presently envisaged, thelower electrode may be diffusion, poly or barrier metals (e.g., titaniumnitride ("TIN"), titanium-tungsten ("TiW"), etc.) or high temperaturesilicide which provides very high flexibility for process integrationand potential for smaller product die size than current ONO basedantifuse products. The upper antifuse electrode may be Poly or metalswhich is also very flexible for process integration and manufacturing.

The temperature constraints on the bottom electrode materials are (1)for metals, not to exceed about 420° C.; (2) for high temperaturesilicide, not to exceed about 750° C.; and (3) for Poly or diffusion,not to exceed about 1000° C. These constraints are due to the hightemperature causing possible diffusion of the electrode material intolower layers of the semiconductor device which could result in devicefailure.

Presently preferred is to carry out device processing in the range of600°-800° C. so that the highest quality films, particularly nitridefilms, may be deposited.

The dielectric layer of the antifuse material layer (18 and 20 inFIG. 1) may be formed of nitrides, oxides or combinations of nitridesand oxides. This structure permits the fabrication of controllableasymmetrical antifuses to meet product needs. Controllable asymmetricalantifuses will provide different voltages of the antifuse sandwich whenprogrammed from different electrodes (i.e., top electrode programmingvs. lower electrode programming). When antifuses on a chip areprogrammed, it is often desirable to apply a programming voltage to oneof the electrodes, e.g., the top electrode, hold the bottom electrodesof the antifuses to be programmed at a low voltage relative to the topelectrode, and hold the bottom electrodes of the antifuses that are notto be programmed at an intermediate voltage. Pulsing and AC soakingtechniques may also be used. Nevertheless, with respect to the antifusesthat are not to be programmed, they are exposed to some degree of stressduring the programming operation of the antifuses to be programmed. Bymaking the antifuses weaker in the direction of the applied programmingvoltage, stress is reduced on the antifuses not being programmed becausethe ones slated to be programmed program faster.

The Poly layer 22 may be doped or undoped polysilicon, as desired. Bylightly doping the polysilicon, its breakdown voltage decreases. Lightlydoped polysilicon is more resistive than heavily doped polysilicon(which has a sheet resistance of about 30 ohms per square) and lessresistive than undoped polysilicon (with a sheet resistance of in excessof 1 Megohm per square). Thus heavily doped polysilicon is moreconductive and may be used for an antifuse electrode. By increasing thethickness of the polysilicon layer, its breakdown voltage increases.Increasing the thickness of the polysilicon layer also decreases thecapacitance presented by the antifuse (the antifuse is, in effect, aparallel plate capacitor and increasing the distance between the platesdecreases capacitance). Thus the antifuse may be designed to have aparticular programming voltage without paying the price of increasedcapacitance for reduced breakdown voltage. This can be achieved bysimply increasing the doping level of the Poly layer without decreasingthe thickness of the antifuse material layer. As a result, the designernow has an added dimension available with which to design antifuses.

Polysilicon is a non-TDDB film. It does not exhibit TDDB behavior. As aresult, placing a layer of Poly in the antifuse material layer providesa barrier through which a TDDB failure cannot propagate. As a result, noTDDB failures are to be expected in optimized D/P/D antifuses.

It is to be understood that the present invention is not limited to onlyD/P/D embodiments. It is also possible to make use of the invention in astructure such as a D/P/D/P/D antifuse material layer, (as shown at 14Bin FIG. 3) a D/P/D/a;Si/D antifuse material layer, and other versionsand iterations of the foregoing.

A presently preferred embodiment of the present invention has aprogramming voltage range of about 6 volts to about 100 volts and afirst dielectric layer formed of a nitride of thickness in the range of10 Å-200 Å, a lightly doped Poly layer of thickness in the range of 50Å-1000 Å, and a second dielectric layer formed of a nitride of thicknessin the range of 10 Å-200 Å. Nitride has a breakdown voltage of about 5volts per 100 Å, oxide has a breakdown voltage of about 15 volts per 100Å and the breakdown voltage of the lightly doped Poly is dependent uponthe doping level and would be known to those of ordinary skill in theart. Typical dopants are Arsenic, Phosphorous and Boron as is well knownto those of ordinary skill in the art. The dopants can be added byconventional means such as by ion implantation, in situ doping or POCl₃doping procedures as are known to those of ordinary skill in the art.

Where it is desirable to add an a-Si layer as discussed above, apresently preferred structure (FIG. 3) would have a first dielectriclayer 34 of a nitride of thickness in the range of 10 Å-200 Å, a lightlydoped Poly layer 36 of thickness in the range of 50 Å-1000 Å, a seconddielectric layer 38 of a nitride of thickness in the range of 10 Å-200Å, an a-Si layer 40 of thickness in the range of 50 Å-1000 Å, and athird dielectric layer of a nitride of thickness in the range of 10Å-200 Å. Note here that the breakdown voltage of a-Si is approximately 1volt per 100 Å and the various layer thicknesses are to be adjusted topermit the desired breakdown voltage, currently contemplated in therange of 6 volts-100 volts. It is important in this embodiment (FIG. 3)to construct the Poly layer 36 below the a-Si layer 40 so that thehighest processing temperatures (up to about 950° C.) may be used belowthe a-Si layer 40. Since a-Si layer 40 processing is limited to amaximum temperature of about 560° C., it is best to form this layer 40above the Poly layer 36 and then process the third dielectric layer 42at a temperature not to exceed 560° C. so as not to damage the a-Silayer 40.

Similarly, where a D/P/D/P/D structure first (24), second (26) and thirddielectric layer (28); and is desired, the presently preferredembodiment comprises a first, second and third dielectric layer of anitride of thickness in the range of 10 Å-200 Å, and a first (30) andsecond lightly doped Poly layer (32) of thickness in the range of 50Å-1000 Å, with the doping level selected to achieve the desiredbreakdown voltage as would be known to those of ordinary skill in theart.

While illustrative embodiments and applications of this invention havebeen shown and described, it would be apparent to those skilled in theart that many more modifications than have been mentioned above arepossible without departing from the inventive concepts set forth herein.The invention, therefore, is not to be limited except in the spirit ofthe appended claims.

What is claimed is:
 1. A method of fabricating adielectric/polysilicon/dielectric/a-Si/dielectric antifuse comprisingthe following steps:a. depositing a first dielectric layer over a lowerantifuse electrode; b. depositing a first polysilicon layer over lowerantifuse electrode; c. depositing a second dielectric layer over saidfirst polysilicon layer; d. depositing a layer of a-Si over said seconddielectric layer; e. depositing a third dielectric layer over said a-Silayer; f. depositing an upper antifuse electrode over said thirddielectric layer.
 2. A method according to claim 1 wherein all of therecited steps are carried out at temperatures in the range of 500°C-950° C.
 3. A method of fabricating adielectric/polysilicon/dielectric/polysilicon/dielectric antifusecomprising the following steps:a. depositing a lower antifuse electrode;b. depositing a first dielectric layer over said lower antifuseelectrode; c. depositing a first polysilicon layer over said lowerantifuse electrode; d. depositing a second dielectric layer over saidfirst polysilicon layer; e. depositing a second polysilicon layer oversaid second dielectrin layer; f. depositing a third dielectric layerover said second polysilicon layer; g. depositing an upper antifuseelectrode over said third dielectric layer.
 4. A method according toclaim 3 wherein all of the recited steps are carried out at temperaturesin the range of 500° C-950° C.